1. Field of the Invention
The present invention relates to the field of microwave components and more particularly to the field of microwave chip components.
2. Background Information
A major problem in the field of semiconductor microwave components is component testing. The results of component testing have a poor correlation with respect to the operation of the tested components in an actual system. This low correlation is a result, in part, of difficulties in obtaining high quality, repeatable connections between a test system and a microwave component which is not bonded to the test system. Temporary bonding of a component to a test system for testing purposes is not feasible because such bonds can not be reworked and thus, the tested component can not be used in a system after testing.
Another problem is the low yield of components which actually meet specifications. A number of factors contribute to this low yield. One of the major contributors is the small size of microwave devices embodied in semiconductor chips and the effects that small variations in the structure of those devices have on the electrical operating characteristics of those components.
The monolithic microwave integrated circuit (MMIC) which is normally fabricated in gallium arsenide contains a plurality of devices which together provide an overall transfer function or other electrical operating characteristics which are useful in microwave systems. Because of fabrication tolerances and other effects, the yield of MMICs is relatively small. In many cases, MMICs are operational but do not meet the fairly tight specifications on their operating characteristics which are required in order for systems assembled from those MMICs to operate within their own specifications. This is a separate problem from the problem of an inability to accurately measure the operating characteristics of such components prior to their assembly into final systems.
Another problem with microwave components in general is the great sensitivity of their operating characteristics to the environment in which they are disposed. The operation of such devices, especially GaAs devices and components are extremely sensitive to the presence of a high dielectric constant material on or directly adjacent to their surface. This sensitivity is so great, that a number of microwave device producers refuse to allow any dielectric material whatsoever (not even a passivating layer of glass) to be disposed on the surface of a GaAs device.
The related application Ser. No. 07/504,803 provides a solution to the problem of testing microwave components when those components are to be assembled into systems in accordance with related application Ser. No. 07/504,821 or packaged in accordance with application Ser. No. 07/504,760. These related applications solve the problem of testing microwave components and assembling them into systems with reasonable yields through a process of selecting components which, in fact, have desired operating characteristics or have operating characteristics which can be brought within specifications by modifying the conductors of a high density interconnect structure with which those devices are packaged. This compensates for device characteristic deviations from specifications as measured during testing. Unfortunately, such techniques cannot salvage operative microwave components whose characteristics are too far outside specifications. Further, such techniques can be cumbersome and are dependent on the inclusion in the package of modifiable high density interconnect structures. There is a need for a means of salvaging microwave components which are operative but do not meet their specifications.
A high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of electronic systems. For example, an electronic system such as a micro computer which incorporates 30-50 chips can be fully assembled and interconnected on a single substrate which is 2 inch long by 2 inch wide by 0.050 inch thick. Even more important, this interconnect structure can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where as many as 50 chips having a cost of as much as $2,000.00, each, may be incorporated in a single system on one substrate. This repairability is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 25-100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM.RTM. from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to the softening point of the ULTEM.RTM. polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C. depending on the formulation used) and then cooled to thermoplastically bond the individual components to the substrate. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E.I. du Pont de Nemours Company, which is .apprxeq.0.0005-0.003 inch (.apprxeq.12.5-75 microns) thick is pretreated to promote adhesion and coated on one side with the ULTEM.RTM. polyetherimide resin or another thermoplastic and laminated across the top of the chips, any other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are laser drilled in the Kapton.RTM. and ULTEM.RTM. layers in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization layer which is deposited over the Kapton.RTM. layer extends into the via holes and makes electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the Patents and Applications which are listed hereinafter.
In this manner, the entire interconnect structure can be fabricated from start to finish (after definition of the required conductor patterns and receipt of the electronic components) in as little as .apprxeq.8-12 hours.
This high density interconnect structure provides many advantages. Included among these are the the lightest weight and smallest volume packaging of such an electronic system presently available. A further, and possibly more significant advantage of this high density interconnect structure, is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes typically require the prepackaging or flip-chip mounting of each semiconductor chip, the design of a multilayer circuit board to interconnect the various packaged chips, and so forth. Multilayer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only thing which must be specially pre-fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, other than the requirement that the substrate have appropriate cavities therein for the placement of the semiconductor chips so that the interconnect surface of the various chips and the substrate will be in a single plane. In the HDI process, the required cavities may be formed in an already fired ceramic substrate by conventional, ultrasonic or laser milling. Other compatible substrate materials may also be used. This milling process is straightforward and fairly rapid with the result that once a desired configuration for the substrate has been established, a corresponding physical substrate can be made ready for the mounting of the semiconductor chips in as little as 1 day and typically 4 hours for small quantities as are suitable for research or prototype systems to confirm the design prior to quantity production.
The process of designing an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate normally takes somewhere between one week and five weeks. Once that interconnect structure has been defined, assembly of the system on the substrate may begin. First, the chips are mounted on the substrate and the overlay structure is built-up on top of the chips and substrate, one layer at a time. Typically, the entire process can be finished in one day and in the event of a high priority rush, could be completed in four hours. Consequently, this high density interconnect structure not only results in a substantially lighter weight and more compact package for an electronic system, but enables a prototype of the system to be fabricated and tested in a much shorter time than is required with other packaging techniques.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sep. 27, 1989, now U.S. Pat. No. 5,154,793, issued Oct. 13, 1992, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 310,149, filed Feb. 14, 1989, now U.S. Pat. No. 4,894,115, issued Jan. 16, 1990, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, now abandoned, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, now U.S. Pat. No. 4,878,991, issued Nov. 7, 1989, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, now abandoned, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sep. 27, 1988, now U.S. Pat. No. 5,019,535, issued May 28, 1991, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, now U.S. Pat. No. 5,019,535, issued May 28, 1991, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 253,020, filed Oct. 4, 1988, now U.S. Pat. No. 4,960,613, issued Oct. 2, 1990, entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, now U.S. Pat. No. 4,884,122, issued Nov. 28, 1989, entitled "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 8, 1988, now abandoned, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,638, filed Aug. 23, 1988, now U.S. Pat. No. 4,882,200, issued Nov. 21, 1989, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, now abandoned, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, now U.S. Pat. No. 4,933,042, issued Jun. 12, 1990, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, now U.S. Pat. No. 4,899,153, issued Jan. 30, 1990, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application Ser. No. 289,944, filed Dec. 27, 1988, now U.S. Pat. No. 4,988,412, issued Jan. 29, 1991, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, now abandoned, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, now abandoned, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 07/459,844, filed Jan. 2, 1990, now U.S. Pat. No. 5,127,998, issued Jul. 7, 1992, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 07/457,023, filed Dec. 26, 1989, now U.S. Pat. No. 5,258,920, issued Nov. 2, 1993, entitled "Locally Orientation Specific Routing System" by T. R. Haller, et al.; U.S. patent application Ser. No. 456,421, filed Dec. 26, 1989, now U.S. Pat. No. 5,169,678, issued Dec. 8, 1992, entitled "Laser Ablatable Polymer Dielectrics and Methods" by H. S. Cole, et al.; U.S. patent application Ser. No. 454,546, filed Dec. 21, 1989, now abandoned, entitled "Hermetic High Density Interconnected Electronic System" by W. P. Kornrumpf, et al.; U.S. patent application Ser. No. 07/457,127, filed Dec. 26, 1989, now U.S. Pat. No. 5,040,047, issued Aug. 13, 1991, entitled "Enhanced Fluorescence Polymers and Interconnect Structures Using Them" by H. S. Cole, et al.; and U.S. patent application Ser. No. 454,545, filed Dec. 21, 1989, now abandoned, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al. Each of these Patents and Patent Applications is incorporated herein by reference.